The fundamentals of the MRI experiment are well known. Briefly (and hopefully without undue oversimplification), in a typical MRI system an object 10 (see FIG. 2) to be imaged (e.g., a portion of the human body) is placed in an external static magnetic field gradient. Protons within the object tend to align their spins in accordance with the magnetic field direction. The object is excited by one or more RF excitation pulses of appropriate frequency, timings and durations (as one example, so-called "spin-echo" type pulse sequences may be used). The RF excitation pulses generated at the Larmour frequency cause the protons to precess their spins. When each RF pulse is switched off, the nucleii precess back toward their equilibrium position and in this relaxation process emit an NMR response that can be detected by an RF receiver.
As is well known, different pulse sequences can be used to obtain different results. A pulse sequence generator (hereafter "sequencer") portion of the NMR system (e.g., often a high-speed piece of hardware based on a bit slice processor architecture) provides the sequence of control signals that controls the operation of the RF transmitter(s), RF receiver(s) and gradient magnet(s). The sequencer must reliably provide a high degree of flexibility (e.g., to provide generation of different desired pulse sequences) as well as adequate time resolution and other important features.
Briefly, a sequencer typically comprises a sequential state machine, with each different state providing different output control signals to control different portions of the NMR equipment (e.g., RF transmitter and receiver, gradient coils, etc.). The "next state" to which the sequencer transitions is typically determined by the sequencer previous state. The time at which the transition occurs is generally variable (since different NMR equipment "states" last for different durations within a typical NMR pulse sequence) and may also be determined by the previous state.
The following is a non-exhaustive listing of some possibly representative prior patents and articles relating to NMR sequencers:
Hoenninger III U.S. Pat. No. 4,707,661 (1987); PA0 Clark, "Pulsed Nuclear Resonance Apparatus", 35 Review of Scientific Instruments No. 3, pp. 316-33 (March 1964); PA0 Dick, "A Pulse Programmer For High-Power Nuclear Resonance", 9, pp. 1054-56 Journal of Physics E: Scientific Instruments (1976); PA0 Conway et al, "Circuit for a Digital Pulse Programmer", 48 Rev. Sci. Instrum. No. 6, pp. 656-60 (June 1977); PA0 Caron, "A New Programmable Timer Designed For Pulsed NMR", 31 Journal of Magnetic Resonance 357-62 (1978); PA0 Case et al, "Versatile Pulse Sequence Generator for Pulse NMR", 35 Journal of Magnetic Resonance 439-45 (1979); PA0 Dart, "Highly Flexible Pulse Programmer for NMR Applications", 51(2) Rev. Sci. Instrum. 224-28 (February 1980); PA0 Thomann et al, "Digital Pulse Programmer for an Electron-spin-resonance Computer-controlled Pulsed Spectrometer", 55(3) Rev. Sci. Instrum. 389-98 (March 1984); PA0 Jensen et al, "A Universal Pulse Programmer for NMR Imaging", Proceedings of the Third Annual SMRM 379 (1984); PA0 Sidky et al, "State-machine Digital Pulse Generator", 59(5) Rev. Sci. Instrum. 806-10 (May 1988); and PA0 Wachter et al, "Enhanced State-machine Pulse Programmer for Very-high-precision Pulse Programming", 59(10) Rev. Sci. Instrum. 2285-89 (October 1988).
The Hoenninger patent describes a microcoded sequencer having a 96-bit microcode format including an opcode and associated branch address, a time duration, and various control fields. See also the Sidky et al, Caron et al, Wachter et al and Dart et al articles.
Gating an NMR sequencer transition on an external trigger signal is generally known. Such gating may be used to alter the timing of the sequencer (e.g., to cause it to "wait" at a particular point in an NMR pulse sequence until a certain event occurs).
For example, the Dick article describes an external trigger pulse input that "may alternatively be used to initiate only the continuous pulse train."
See also Dart et al, which teaches in FIG. 1 an "external trigger" signal applied through a one-shot and an AND gate to the "start" input of a clock generator and output register of a sequencer. In the Dart et al arrangement, an instruction with a bit 15="0" causes instruction fetching to stop until the next PULSE ENABLE pulse--thus delaying the output of a pulse until an external trigger input goes positive. Dart explains that such an instruction is normally used to set the rate at which a pulse sequence will be repeated.
Prior art MRI equipment marketed by Diasonics MRI division (and now being marketed by Toshiba of America MRI) includes a writeable control store micro-programmed sequencer which accepts an external gating signal. A programmable rate clock controls the time duration of each state in response to a corresponding microinstruction field. A gating circuit within this programmable rate clock precisely alters the normal operation of the programmable rate clock so as to cause the timing of the sequencer to become dependent on the occurrence of an incoming pulse (transition) applied to an "external gate" input.
This external gate signal may be provided by any desired apparatus (e.g., a patient-operated "breath switch", a cardiac cycle detecting cuff, a "back up" push button switch, etc.). A WAIT bit field is provided within a micro-instruction as a control field. This WAIT bit specifies whether the current state is to be gated on receipt of a negative-going external gating pulse edge. When the WAIT bit is asserted, the normal output of programmable rate clock is nullified and the current state persists until a valid external gating pulse is received. Depending upon the contents of an instruction field portion of the microinstruction, a branch to "back up" to an earlier point in the pulse sequence may be effected upon receipt of the external gating pulse, or other desired action (e.g., continue) may be taken.
FIG. 1 is a detailed schematic diagram of circuitry within the prior art Diasonics (Toshiba America) MRI sequencer that relates to the externally gated programmable rate clock. When a delay block 164 outputs a load control signal "CNTLD", a programmable counter 170 is loaded from the micro-instruction "clock time" field 152b outputted by a writeable control store ("WCS") 150 (this output of the WCS may first be latched in a temporary holding asynchronous latch before being loaded into the counter 170).
If the WAIT bit field 152d outputted with the micro-instruction clock time field 152b from WCS 150 is unasserted (logic level 0; indicating that the instruction is not to "wait" until an external gating pulse edge is received), inverter 181 applies a logic level 1 to the input of OR gate 180 (thus blocking any transitions applied to the other input of this OR gate by the "/EXT. GATE" line 176 and causing the output of OR gate 180 to remain fixed at logic level 1). Thus, the Q output of external gate latch is at logic level 1 and the output of AND gate 184 remains at logic level 1 until programmable counter 170 generates an active low pulse.
Similarly, the Q output of WAIT bit latch 172 remains at logic level 0--thus permitting OR gate 174 to pass the active low /zero count output of programmable counter 170 when it occurs. The active low /zero count signal is applied to the input of AND gate 184, causing the /INC (active low) signal to be asserted. Upon the zero-to-one transition of the /zero count signal, the /INC signal undergoes a similar zero-to-one transition--causing clock delay block 186 (effectively a falling edge sensitive one-shot) to produce an active low /CNTLD signal. This /CNTLD signal controls programmable counter 170 to load the microinstruction field 152b from the writable control store and to begin timing the duration of the next state. /CNTLD also loads WAIT bit latch 172 with the WAIT bit field.
Assume now that the WAIT bit field 152d outputted with the micro-instruction clock time field 152b from WCS 150 is asserted (logic level 1) to indicate that the instruction is to wait until an external gating pulse edge is received. WAIT bit latch 172 is thus set by clock CNTLD (i.e., its output takes on a logic level 1)--thereby forcing OR gate 174 to have a logic level 1 input. With this logic level 1 input being applied to OR gate 174, the OR gate blocks the active low /zero count output of programmable counter 170. Counter 170 begins counting down from its preset value (to time the duration of the current state) and produces a /zero count output when it has counted down to zero (thereby timing the delay specified by the clock time field 152b previously loaded into it). This /zero count signal is applied by counter 170 to the other input of OR gate 174. However, since the WAIT bit latch 172 is set, the /zero count signal has no effect on the output of OR gate 174.
Thus, when the time specified by the micro-instruction clock time field 152b elapses, the WAIT bit latch Q output causes the output of OR gate 174 to remain high (and the corresponding input of AND gate 184 to also remain high) regardless of the state of the counter 170 /zero count output. The output of gate 184 will not change state under these circumstances until an external active-low gating pulse having a duration longer than the period of the sequencer system clock period (e.g., 0.5 microseconds) is received--as will now be explained.
An external gate connector line 176 (labelled "/EXT GATE") is normally pulled up by a pull-up resistor 178 to logic level 1. A logic level 1 on the WAIT bit causes inverter 181 to produce a logic level 0 signal level--thus permitting OR gate 180 to pass signals present on the /EXT GATE line.
When a transition (e.g., caused by closing and opening a switch connected to the connector 177) is applied to /EXT GATE line 176 while the WAIT bit is ON (either before or after the counter 170 has counted down), the output of OR gate 180 follows the /EXT GATE signal. An active low output of OR gate 180 is synchronized by external gate latch 182 (a synchronous D flip-flop in the preferred embodiment) upon the occurrence of the next positive-going edge of the system clock signal CLK1 to provide a logic level 0 active level on the Q output of the external gate latch 182. The resulting active low output of the external gate latch Q output 182 forces the output of AND gate 184 low, thus causing an (active low) increment signal /INC to be generated. This /INC signal remains at logic level 0 until the /EXT GATE signal returns to logic level 1. /INC causes the transition to the next microinstruction state. Clock delay circuit 164 produces a short /CNTLD active low pulse to cause the counter 170 to load and to load WAIT bit latch 172 (and to cause OR gate 175 to block the /zero count output of programmable counter 160 when it is loaded). A sequencer state transition on the next /ZERO CNT assertion thus may not occur unless the /EXT GATE signal exhibits a rising edge transition before /ZERO CNT is asserted.
The external gating arrangement shown in FIG. 1 has been highly successful in reducing motion artifacts within MRI images. However, further improvements are possible.
The FIG. 1 gating arrangement was designed with the concept of providing gated and ungated versions of certain microprograms in mind. Often, however, exactly the same pulse sequence might be operated in gated and ungated modes. When the prior art (FIG. 1) gating arrangement was designed, it was assumed that a gated version (i.e., WAIT bit asserted) of a particular microprogram would be run if externally gated operation was desired and that a non-gated (i.e., WAIT bit unasserted) version would be executed if no external gating was desired.
However, it has now been discovered that rather than writing some routines that are gated based on an external gating signal and writing other routines that are not gated, it may be desirable to use exactly the same microprogram for both gated and non-gated operations--and provide a mechanism related to the external gating system itself specifying or controlling at time of execution whether or not the pulse sequence specified by the microprogram is to be externally gated.
Thus, a microprogram could be written with external gating capability, but the gating function might be only selectively enabled (e.g., based on whether or not an external gating apparatus is connected at the time the microprogram is executed). By initially writing microprograms to include an external gating operation and by providing a means by which the gating can be selectively enabled or disabled at time of execution, the quantity of code to be written and maintained can be significantly decreased--since there is no longer a need to provide gated and ungated versions of the same microprograms. Moreover, overall flexibility and functionality can be significantly increased because even microprograms that may rarely be externally gated can nevertheless be written in a manner that provides external gating (and whether or not the microprogram is externally gated will depend on gating conditions existing at time of execution).
It will be apparent to those skilled in this art that the FIG. 1 external gating arrangement is not particularly suited for allowing a given microsequence to be executed in either a gated mode or an ungated mode. As mentioned, the FIG. 1 circuit is sensitive to the occurrence of a rising edge transition of the /EXT GATE signal. If the /EXT GATE signal is asserted all of the time, no such transition will occur. Once the WAIT bit is asserted HIGH by the writable control store, the Q output of external gate latch 182 changes state on the following edge of clock signal CLK1. With /INC held LOW, no further /CNTLD signals are generated unless a transition occurs on the /EXT GATE signal.
Thus, once the WAIT bit is asserted HIGH, the sequencer will wait for a rising edge transition in the external gating signal before the next state is allowed to complete. If an external gating signal transition does not occur, the sequencer simply "hangs"--a highly disadvantageous operating condition if the operator does not intend external gating to be in effect.
Sometimes, an external gating pulse generator has been used with systems employing the transition-sensitive external gating circuit arrangement shown in FIG. 1 in order to avoid these problems. It is possible to prevent the sequencer from "hanging" by connecting to the external gating input a clock pulse generator producing a periodic clock pulse signal of an appropriate frequency. Such a clock pulse generator has the effect of guaranteeing that an external gating pulse will be provided shortly after the programmable counter 170 counts down to zero and the INC signal is held LOW. The system continues to gate in response to external gate signal transitions, but the external clock generator simply guarantees that an external gate signal transition will occur before the sequencer waits more than a negligible amount of time.
Unfortunately, it is highly inconvenient for the operator to have to connect an external clock generator to the gating input whenever no gating is desired. Such an external clock generator provides another point at which failure can occur and another thing for the operator to remember to check when a failure mode is exhibited.
It would be highly desirable to eliminate this extra source of operator error and possible cause of failure. It would also be highly desirable to permit the system to execute the microinstructions programmed for gating in either a gated mode or in an ungated mode--depending merely upon whether or not an external gating device is coupled to the external gating input.
The present invention provides an improved external gating technique for a microcoded NMR sequencer which is sensitive to the level (rather than to transitions) of the external gating signal.
In accordance with one aspect of the present invention, the sequencer detects the level of the external gating signal very soon after it has first begun executing an instruction specifying a wait on external gating. One external gating signal level specifies that the instruction with WAIT asserted or WAIT instruction is to be ignored, and another external gating signal level specifies that a wait on an external gating event is to occur. If the level of the external gating signal is such that the WAIT bit asserted is to be ignored, the sequencer state transition occurs immediately without waiting for the external gating event. The "clock time" field is ignored. Microinstruction routines can be designed (i.e., by appropriate placement of the WAIT instruction) such that the short delay does not adversely affect the NMR experiment--and the experiment may thus proceed essentially continuously.
On the other hand, if a WAIT instruction is encountered and the external gating signal is at a level indicating that external gating is active, the sequencer will wait until the level of the external gating signal changes before going to the next state.
Thus, the very same WAIT instruction is treated in two different ways by preferred embodiment sequencer depending upon the level of the external gating signal--with the external gating signal level effectively disabling the WAIT instruction state if external gating is not desired. In this way, the microinstruction sequences containing WAIT instructions may be operated in either a gated or a non-gated mode--depending upon the level of the external gating input that exists at the time the sequencer executes the instructions.